Chinese translation for "gate delay"

门信号延迟
门延迟
选通延迟

Related Translations:

gate:  n.1.大门，扉，篱笆门，门扇。2.闸门；城门；洞门；隘口，峡道。3.【冶金】浇注道，浇口，切口；【无线电】门电路，选通电路，选通脉冲，启开脉冲，时间限制电路。4.(运动会、展览会等的)门票收入；观众数；入场费。5.〔英国〕伦敦 Billingsgate, Newgate 等的略称。6.锯架。7.电影放映机镜头窗口。8.〔俚语〕解雇。短语和例子a folding gate折

gates:  n.盖茨〔姓氏〕。

gating:  浇注系统门控选通, 控制选通开启控制入型口异界之门遮没

gated:  网关常驻程序网关守护神选通的,门控的

gate ved gate:  玫瑰仙子金曲集相对的城门

gate gated pattern:  带浇口的铸模

amplitude delay:  振幅延迟

balance delay:  平衡迟误

delay helix:  螺旋延迟线

delay penalty:  延误判罚逾期罚款

Example Sentences:

	1.	Trigger gate delay 触发门脉冲延迟
	2.	The problem in high speed signal process , such as parasitic parameter and gate delay is also the difficulty hi the research 生成高速，稳定的时钟信号是本课题的目标。高速信号处理所遇到的常见问题，如寄生参数，门电路延迟是设计难点。
	3.	Due to the subtle error among different manufacturing equipment , the gate delay of circuits is different and varies in a given scope , which induces the time uncertainty of the waveform 由于制造设备本身存在微小误差，具体门的延时并不相同，而是在一定范围内变化，引起波形变化的时间不确定。
	4.	This paper constructs a stable rlc interconnect model based on the first three moments of the node admittance , and discusses its application to interconnect delay and logic gate delay estimation 摘要基于rlc互连树节点导纳的低阶矩构建了一种稳定的互连模型，并讨论了它在互连树延时和逻辑门延时估计中的应用。
	5.	When the silicon technology comes to deep sub - micron level , the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency , the allowable errors become smaller , and the influence of the transmission delay gets bigger , which increase the difficulty of the circuit design 在深亚微米制造技术中，芯片互连线延迟超过门延迟，而且随着集成电路工作频率的提高，允许的时序容差变小，传输延迟的影响加大，设计工作难度增加。
	6.	An algorithm of path - based timing optimization by buffer insertion is presented . the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation . and heuristic method of buffer insertion is presented to reduce delay . the algorithm is tested by industral circuit case . experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied 提出了一种基于路径的缓冲器插入时延优化算法,算法采用高阶模型估计连线时延,用基于查表的非线性时延模型估计门延迟.在基于路径的时延分析基础上,提出了缓冲器插入的时延优化启发式算法.工业测试实例实验表明,该算法能够有效地优化电路时延,满足时延约束
	7.	In this paper an fault simulator for iddt testing is presented , which can detect concurrently the multi - faults . due to the subtle error among equipment manufacturing , the gate delays of circuits are not the same but range within limits . which induces the uncertainty of the waveform transforming time 本文从故障激活的条件入手,利用五值逻辑,对瞬态电流测试中的延时变化进行波形分析和波形计算,采用并发模拟算法,编程实现了一个iddt测试的故障模拟器。实际电路中由于制造工艺的限制,逻辑门的延时并不相同,而是在一定范围内变化,引起波形变化的时间不确定。

Similar Words：

"gate cutting" Chinese translation, "gate cutting machine" Chinese translation, "gate d re" Chinese translation, "gate dam" Chinese translation, "gate damper" Chinese translation, "gate delay time" Chinese translation, "gate density" Chinese translation, "gate detector" Chinese translation, "gate diagram" Chinese translation, "gate dielectric" Chinese translation